The present invention is related to data transactions. More particularly, the present invention is directed to managing memory controller hub transaction ordering in systems supporting bus communication.
Many programming tasks, especially those controlling intelligent peripheral devices common in Peripheral Component Interconnect (PCI) systems, require specific events to occur in a specific order. If the events generated by the program do not occur in the hardware in the order intended by the software, a peripheral device may behave in a totally unexpected way. PCI transaction ordering rules provide hardware the flexibility to optimize performance by rearranging certain events that do not affect device operation, yet strictly enforce the order of events that do affect device operation.
One performance optimization that PCI systems are allowed to do is the posting of memory write transactions. Posting means the transaction is captured by an intermediate agent; e.g., a bridge from one bus to another, so that the transaction is captured by an intermediate source before it actually completes at its intended destination. This allows the source to proceed with the next operation while the transaction is still making its way through the system to its ultimate destination.
While posting improves system performance, it complicates event ordering. Since the source of a write transaction proceeds before the write actually reaches its destination, other events that the programmer intended to happen after the write may happen before the write.